The present invention relates to semiconductor memory cell arrays, and more particular to a hybrid dynamic random access memory (DRAM) cell array which is ultra-scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V. The present invention also relates to a processing scheme that is capable of forming the above-mentioned hybrid DRAM cell array.
As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path holes flowing into and out of the portion of the P-well above the buried-strap region.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM memory arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM memory cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM memory cells beyond 110 nm is expected to be limited by floating-well effects.
An illustration of a dominant floating-well dynamic leakage mechanism that limits scalability of prior art vertical DRAM memory arrays is shown in FIG. 1. Specifically, at a time indicated by point A of FIG. 1 and during a long period of about 5-100 ns of repeated writing of a xe2x80x9c1xe2x80x9d to other memory cells on the bitline, the P-well of an unselected cell storing a xe2x80x9c1xe2x80x9d may leak up towards Vblh, as the exiting of holes is restricted by parasitic JFET. Leakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo xe2x80x9cFloating-Body Effectxe2x80x9d.
Insofar as time interval B-C is concerned, the N+ bitline diffusion to P-well barrier is lowered by a downward swing of Vblh. Electrons emitted from the bitline diffusion region are collected by the storage node resulting in the formation of a parasitic bipolar transistor, QB, (PWint is a floating base) within the memory cell array.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in xe2x80x9cFloating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)xe2x80x9d,. Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, Oct. 1996.
An illustration of the storage capacitor voltage vs. the voltage in the portion of the P-well isolated by the depletion region from the buried-strap outdiffusion, as the bitline is cycled, is shown in FIG. 2. When the bitline is held at Vblh, the isolation portion of the P-well leaks up towards the voltage of the adjacent diffusions. With subsequent cycling of the bitline between 0.0 and Vblh, the dynamic charge loss mechanism results in charge pumping which discharges the storage capacitor. Between data refresh, greater than 106 bitline cycles are possible, which is sufficient to discharge the storage capacitor.
One possible solution to the scalability limitation resulting from floating-well effects, which has not yet been implemented in existing memory structures, includes a contact to the portion of the P-well above the buried-strap outdiffusion region. If such a memory structure is possible, it must be provided in a manner that does not negatively impact cell density, does not degrade junction leakage, and does not add to the fabrication complexity. To date, applicants are unaware of a prior art vertical DRAM memory structure of this type that overcomes the scalability limitation resulting from floating-well effects.
The present invention provides a memory cell structure and processing scheme that provides a contacted body and maintains low junction leakage, while actually reducing fabrication cost, retarding the onset of scalability limitations due to floating-well effects to approximately 60 nm groundrules.
One object of the present invention is to provide a hybrid memory cell array (6F2), which avoids strap-to-strap leakage problems to a minimum feature size, F, of about 60 nm at operating voltages of Vblh of about 1.5 V.
Another object of the present invention is to provide a hybrid memory cell array wherein the floating-well effects are substantially eliminated.
A further object of the present invention is to provide a hybrid memory cell array that has tighter support groundrules.
A still further object of the present invention is to provide a hybrid memory cell array in which low-aspect ratio shallow isolation trench (SIT) regions are employed.
A yet further object of the present invention is to provide a hybrid memory cell array having improved narrow width effects.
An even further object of the present invention is to provide a hybrid memory cell array wherein the spaces between the SIT regions may be greater than 1 F without critical overlay in the array.
These and other objects and advantages are achieved in the present invention by providing a vertical DRAM memory cell array in which a contact to the P-well above the buried-strap outdiffusion region is provided. Specifically, the inventive hybrid memory cell array comprises:
a plurality of vertical memory cells which are arranged in rows and columns, each vertical memory cell being formed in a storage trench that is present in a P-well of a Si-containing substrate and each vertical memory cell includes a MOSFET region formed over a storage capacitor, said MOSFET region and said storage capacitor being electrically connected by a one-sided buried-strap outdiffusion region, said one-sided buried-strap outdiffusion region being confined to a substantially center portion of the storage trench; and
shallow isolation trench regions located between adjacent columns of memory cells, each of said shallow isolation trench regions having a depth that is substantially above said one-sided buried-strap outdiffusion region thereby not cutting into said one-sided buried-strap outdiffusion region, yet being deep enough to isolate adjacent bitline diffusion regions that abut each vertical DRAM cell.
The inventive memory cell array also includes wordlines that are formed above each vertical DRAM cell, borderless bitline contacts that are in contact with said bitline diffusion regions and bitlines that are formed above and perpendicular to the wordlines. In one embodiment of the present invention, the bitlines have approximately a 3 F pitch associated therewith and the cell is approximately a 6 F2 memory cell.
The present invention also provides a process of fabricating the above-mentioned memory cell array. Specifically, the inventive process includes the steps of:
(a) forming at least one deep trench capacitor in a Si-containing substrate, said deep trench capacitor including at least a:deep trench polysilicon material;
(b) patterning said deep trench polysilicon material using at least a hard mask to cover a middle portion of the deep trench capacitor and selectively recessing exposed portions of said deep trench polysilicon material to a depth below that of a strap opening to be subsequently formed;
(c) filling said recessed portion of said deep trench polysilicon material with an oxide and planarizing said oxide stopping on said hard mask;
(d) removing said hard mask to expose said middle portion of said deep trench capacitor and selectively etching the exposed deep trench polysilicon material to a depth that is above said oxide fill;
(e) filling said etched middle portion with a photoresist material and planarizing said photoresist material stopping on said substrate;
(f) removing said photoresist material from said middle portion of said deep trench capacitor so as to expose a portion of said deep trench polysilicon material and selectively forming bitline diffusion regions about said deep trench capacitor above regions wherein said strap opening will be subsequently formed;
(g) providing said strap opening in said deep trench capacitor and forming a one-sided buried-strap outdiffusion region through said strap opening, said one-sided buried-strap outdiffusion region being confined to a substantially center portion of the deep trench capacitor;
(h) forming a trench oxide layer on said exposed portion of said deep trench polysilicon material and forming a gate conductor on said trench oxide layer; and
(i) forming shallow isolation trench regions adjacent to said deep trench capacitor, wherein said shallow isolation trench regions have a depth that is substantially above said one-sided buried-strap outdiffusion region thereby not cutting into said one-sided buried-strap outdiffusion region, yet being deep enough to isolate adjacent bitline diffusion regions that abut each vertical DRAM cell.
The inventive process further includes forming wordlines above said deep trench capacitor, forming borderless bitline contacts adjacent to said wordlines and forming bitlines above and perpendicular to said wordlines that are in contact with said bitline contacts.
In one embodiment of the present invention, the one-sided buried-strap outdiffiusion region is formed earlier in the process. Specifically, in that embodiment of the present invention, steps (a)-(d) are first performed, then step (g) is performed followed by steps (e), (f), (h) and (i).